Analog subsystem

IM3000 family ADC/DAC specifications

ADC

Pins

Pin  name

Type

Description

VCC

Analog power

3.3V power

VDD1V8

Digital power

1.8V digital supply. Can be connected to 3.3V if digital input signals have 3.3V levels 

VSS

Analog ground

clkin

Digital input

Input clock

ACH<7:0>

Analog  input

Input signals bus

EXTREF

Analog  input

Analog reference for external reference mode

vbg

Analog  input

Bandgap reference voltage 0.7V

ach_sel<2:0>

Digital input

Input multiplexer control bits

adc_diff

Digital input

Differential mode control bit. Should be low for internal reference mode

adc_extref

Digital input

External reference mode control bit

adc_ref2v

Digital input

Internal reference selection control bit. Internal reference is 1V if low, 2V if high

adc_en

Digital  input

vih=1.1V, vil=0.2V

Enable control bit active high

adc_bits

Digital output

Digital conversion of input signal in Pulse Density Modulation


Electrical parameters

Vcc=3.3V, T=25, fclk=10MHz, adc_diff=1, adc_ref2v=0, adc_en=1  unless  otherwise  specified.

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Resolution

Output word width

16

Bits

Power supply voltage

Vcc

3

3.3

3.6

V

Operating temperature

T

junction

­20

100

°C

Input signal bandwidth

B

0

20

kHz

Input capacitance

Cin

4

pF

Offset  error

Input­referred

+/­20

mV

Linearity error

INL

DC

+/­0.06

%FS

Gain error

+/­4

%FS

Clock frequency

fclk

1

10.24

MHz

Sampling rate

fs

40

kHz

SNR

sinus 3kHz 80%FS

80

86

dB

THD

sinus 3kHz 80%FS

65

dB

Pass band ripple

6

dB

Current consumption

Icc

analog circuits

3

5

mA

Settling time (digital output)

full­scale step

4

samples

Wakeup time

Twu

biasing

20

40

us

Detailed description

Operating modes

Differential or single­ended: When control bit adc_diff is high, differential mode is selected. This is the preferred mode for audio applications, as the distortion and PSRR characteristics are better.

External reference: When control bit adc_extrefis high, the external EXTREF reference is used as reference.

Internal reference: When control bit adc_extref is low, an internally generated reference is used. The internal reference is generated from the 0.7V voltage at the vbginput pin. If pin adc_ref2Vis low, the internal reference is 1V, otherwise it is 2V.

Disable mode: When control pin adc_enis low, the cell is disabled. VDD1V8 supply doesn’t need to be up in order to put the cell in disable mode.

Signal source

Input is sampled into a 0.8pF capacitor (nominal) at clkin rate. In order to avoid sampling errors it is recommended that the signal source has output impedance lower than 3 kOhms. Due to the operation of the switched­capacitors circuit, synchronous noise might otherwise add noise to the signal.

Input multiplexing

This cell has 8 multiplexed inputs that can be selected according to the following table:

ach_sel<2:0>

adc_diff=0

adc_diff=1

000

ACH0

ACH0  ­ ACH1

001

ACH1

ACH1  ­ ACH0

010

ACH2

ACH2  ­ ACH3

011

ACH3

ACH3  ­ ACH2

100

ACH4

ACH4  ­ ACH5

101

ACH5

ACH5  ­ ACH4

110

ACH6

ACH6  ­ ACH7

111

ACH7

ACH7  ­ ACH6


Input swing

Input swing range is set according the following table:

adc_ref2V

adc_extref

adc_diff=0: v(vin)

adc_diff=1: v(vinp)­v(vinn)

0

0

0  .. 1V

­0.5  .. 0.5  V

1

0

0  .. 2V

­1  .. 1V

x

1

0  .. extref

­extref/2  .. extref/2

At the lower and upper limits of the input swing, pulse density at the adc_bitsoutput is 12.5% and 87.5% respectively. This ADC converter can be operated slightly outside the specified input swing range without saturating but at the cost of increased quantification noise at the digital output.

Each ACH<7:0> input should stay within VSS an VCC voltage.

In differential mode, input common mode voltage (V(vinp)+V(vinn))/2 can be freely chosen, under the condition that the previous condition is met.

DAC

Pins

Pin name

Type

Description

VCC

Analog power

3.3V power

VDD1V8

Digital power

1.8V digital supply. Can be connected to 3.3V if digital input signals have 3.3V levels

VSS

Analog ground

clkin

Digital input

Clock input signal

bitstream

Digital input

Digital input in Pulse Density Modulation

vbg

Analog input

Bandgap reference voltage 0.7V

enable

Digital input

vih 1.1V, vil=0.2V

Enable control bit active high

vout

Analog output

Converted analog output signal

voutfb

Analog input

Feedback for force/sense connection of output signal

Electrical parameters

Vcc=3.3V, T=25°C, fclk=10MHz, enable=1  unless  otherwise  specified

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Power supply voltage

Vcc

3

3.3

3.6

V

Operating temperature

T

junction

­20

100

°C

Output signal swing

peak­to­peak

1

V

Output DC level

mid­scale

1.5

V

Signal bandwidth

B

20

kHz

Offset error

Output­referred

+/­35

mV

Linearity error

INL

DC

+/­0.06

%FS

Gain error

+/­4

%FS

Clock frequency

fclk

4

10.24

MHz

SNR

sinus 3kHz 80%FS

80

86

dB

THD

sinus 3kHz 80%FS

65

dB

Pass­band ripple

6

dB

Current consumption

Icc

analog circuits

5

7

mA

Load current

source or sink

50

uA

Wakeup time

Twu

biasing

20

40

us

Detailed description

Disable mode: when control pin enableis low, the cell is disabled. VDD1V8 supply doesn’t need to be up in order to put the cell in disable mode.

Output signal swing: Output signal swing is between 1 and 2V when digital input swing is between 12.5% and 87.5% pulse density. This DAC can be operated slightly outside the specified input range at the cost of degraded performance.

Output loading: up to 50uA can be loaded from the output.